Q.29)Tell some of applications of buffer? (asked in verilog Interview)
Wednesday 31 October 2012
Post # 274
A.28)Tie one of xor gates input to 1 it will act as inverter & Tie one of xor gates input to 0 it will act as buffer
Post # 272
at the end of metastable state,the flip-flop settles down to either '1' or '0'.This whole process(see last 2 msgs)is known as metastability.
Post # 270
Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable(Contd…)
Post # 269
amnt of time after the clock edge that same i/p signal has to be held B4 changing it to make sure it is sensed properly at the clock edge.
Post # 267
is the amount of time before the clock edge that the input signal needs to be stable to guarantee it is accepted properly on the clock edge.
Post # 265
A.25)To avoid metastable state, a series of FFs is used (normally 2 or 3) which will remove the intermediate states.
Post # 263
A.24)metastability will happen if the O/P cap is not allowed to charge/discharge fully to the required logical levels.
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