Q.6) What are the limitations in increasing the power supply to reduce delay?
Friday 5 October 2012
Thursday 4 October 2012
Wednesday 3 October 2012
Post # 215
A.4) delay increases. (Any suggestion will be appreciated at jigarforelectronics.blogspot.in)
Post # 214
Q.4)What happens to delay if you increase load capacitance?[This is Interview Questionnaire week for ECE final year student].
Tuesday 2 October 2012
Post # 213
A.3)In order to drive the desired load capacitance we have to increase the size (width) of the inverters to get an optimized performance.
Post # 212
Q.3)Explain sizing of the inverter?(You can have all older posts of E_K from jigarforelectronics.blogspot.in) Thanks for joining.
Post # 211
A.2)The minimum amount of noise that can be allowed on the input stage for which the output will not be effected.
Monday 1 October 2012
Post # 209
A.1)because at the transistor level the mobility of electrons is normally 3times that of holes compared to NOR&thus the NAND is faster gate.
Post # 208
Q.1) Why is NAND gate preferred over NOR gate for fabrication??? (Asked in CMOS/Verilog interview)
Sunday 30 September 2012
Post # 207
E_K is going to start : Interview Questionnaire weeks for ECE final year students as this is the time of campus interview for them. Enjoy
Post # 206
PID controller : proportional–integral–derivative controller is the most commonly used feedback controller.
Post # 205
MOSFET as switch:U need Body diode betwn the drain(to cathode)& the source(to anode),making it able to block current in only 1 direction.
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